Alphawave Semi has taped out a powerful new chiplet subsystem aimed at turbocharging AI performance. Built on TSMC’s cutting-edge 2nm process, the new 36G UCIe IP offers record bandwidth and energy efficiency. The technology marks a major leap in chiplet-based design, a method gaining traction for its ability to boost performance in artificial intelligence (AI) and high-performance computing (HPC). “This isn’t just about speed,” said Mohit Gupta, Senior VP at Alphawave Semi. “It’s about scaling the future of AI workloads efficiently and reliably.” The innovation comes as data center operators and AI developers push for faster, more flexible silicon.
AI Chiplets Built for the Next Era of Processing
The new UCIe IP subsystem enables die-to-die communication at 36 gigabits per second, thanks to nanosheet transistor technology. Developed for TSMC’s 2nm process and integrated with CoWoS® advanced packaging, the system is designed to fuel next-generation AI platforms. UCIe, short for Universal Chiplet Interconnect Express, is an open industry standard that allows different chiplets to talk to each other efficiently. Alphawave’s design complies with UCIe 2.0 and supports multiple protocols like PCIe, CXL, AXI, and CHI.
Its Streaming Protocol D2D Controller adds flexibility for various chip architectures. What makes this tape-out significant is the bandwidth density of 11.8 terabits per second per millimeter. This is vital for handling the growing demand for AI model training and inference. “We’re unlocking a new class of chiplet connectivity,” said Gupta. “This supports higher density and lower power, key for AI and cloud-scale networking.”
Real Results, Real Impact for AI Builders
With this launch, Alphawave Semi becomes one of the first to enable UCIe-based connectivity on a 2nm nanosheet platform. The system is built for scale, opening the door to future 64G UCIe IP that will handle even denser AI models. It also includes features like live per-lane health checks and robust test support, essential for mission-critical AI deployments.
The implications go beyond performance. Lower power usage means lower operating costs, an urgent need for energy-hungry AI data centers. TSMC sees this as a milestone too. “Our partnership with Alphawave shows how advanced silicon and packaging unlock next-gen computing,” said Lipen Yuan, Senior Director at TSMC.
Challenges remain. Adoption of chiplet standards like UCIe requires coordination across hardware and software ecosystems. Reliability at extreme bandwidths also needs continual validation. Still, Alphawave is moving fast, already preparing 64G solutions to meet upcoming AI and HPC demand.
Alphawave Semi Taps a Larger AI Opportunity
Alphawave Semi’s latest chiplet breakthrough shows its growing role in powering the future of AI systems. By connecting tiny chips together on TSMC’s advanced 2nm technology, the company is helping AI platforms run faster and use less energy. As demand for smarter, more powerful computing grows, this kind of flexible design will matter even more. Alphawave’s new solution isn’t just about speed, it’s about building smarter foundations for tomorrow’s AI. With this step, Alphawave strengthens its place in the race to deliver the tools that make AI faster, cheaper, and more scalable for real-world use.
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